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Oceniono. / 5. Na podstawie oceny klientów
SLVS
Half Bridge
VSS Referenced
Bias P
VDR = 1.2V
V
IN+
V
IN-
V
OCM
= 175 mV
V
OUT+
Optional
internal 1005
termination
V
OUT-
ADC12EU050
SNAS444I –JANUARY 2008–REVISED APRIL 2013
www.ti.com
Figure 19. Output Driver Circuit: SLVS
As well as the different output modes, the output drive current can also be controlled via the LVDS Control
Register. The default output drive current is 2.5mA, but this can be increased to 3.5mA or 5mA, depending on
output trace routing and receiver requirements. Power consumption of the ADC12EU050 will increase slightly as
the output driver current is increased.
Termination
The final control feature available in the LVDS Control Register is the choice between internal and external 100Ω
termination. Although the termination is recommended to be as close to the receiver as possible, in some cases
it may be necessary or desirable to perform this termination at the transmitter. Internal 100Ω termination at the
transmitter (the ADC12EU050) is enabled by setting the bit TX_term to 1.
LVDS Output Training Sequences
Often it is necessary to calibrate the LVDS receiver, for example an FPGA or DSP, so that skew between the
eight ADC output channels is minimized. In order to simplify this process, the ADC12EU050 provides three LVDS
training modes, where a pre-defined or custom pattern is output on all eight channels simultaneously. While a
training mode is active, the word and bit clocks are output as usual. In order to select a training mode, the TSEL
bits of the Decimator Control Register (16h) must be programmed via the SPI interface.
There are two pre-defined training patterns, or a custom pattern can be loaded via the SPI into the Serializer
Custom Pattern 0 and 1 Registers (10h and 12h). In order to return to normal ADC operation after skew
calibration, the TSEL bits should be returned to their default value of 00.
22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADC12EU050
- Converter 1
- ADC12EU050 10
- 32 + 4 x DGFa + DGFb 34
- PACKAGE OPTION ADDENDUM 39
- NKE0068A 41
- IMPORTANT NOTICE 44
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